The present invention relates to integrated circuits, and more specifically, to routing the connections between components of an integrated circuit (IC).
Integrated circuit layout, also known as IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. When using a standard process—where the interaction of the many chemical, thermal, and photographic variables are known and carefully controlled—the behavior of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. A layout engineer's job is to place and connect all the components that make up a chip so that they meet all criteria. Typical goals are performance, size, and manufacturability.
Initially, IC design layout was done by hand using opaque tapes and films, much like the early days of PCB design. Modern IC layout is done with the aid of IC layout editor software, or even using EDA (Electronic Design Automation) tools, including place and route tools or schematic driven layout tools. The manual operation of choosing and positioning the geometric shapes is informally known as “polygon pushing”.
Layout design takes a significant amount of time in the overall project schedule. Improving the turnaround time for layout design is key to enhance productivity. One of the major time constraints in the layout process involves the routing of wires between components. Layout turnaround time can be improved by using automated routing provided, for example, by a computer programming.
In custom macro design, the designer typically has a hierarchical schematic with a corresponding hierarchical layout. A hierarchical schematic is based off of base building blocks which are combined to form more complex components. However, due to the hierarchy of the structures, routing techniques currently used are not very efficient.
One approach to reducing the time for routing has been to employ the so-called “random logic macro” (RLM) approach. In the RLM approach, a hierarchical schematic is flattened to create a “flat” circuit. The flat circuit is then routed quickly and easily. This solution, however, suffers from the fact that after the circuit has been “flattened” it becomes hard to read. This is due, in part, to the fact that there are no blocks on the schematic that represent circuit elements that may be easily understood by a human.
Another approach is the custom macro approach. In this approach, the routing is conducted through each level of the hierarchy separately. This process is, however, time consuming and may encounter problems of efficiency in dealing with wiring blockages or other problems that can arise.